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» Improving SHA-2 Hardware Implementations
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82
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MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
15 years 6 months ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
114
Voted
SI3D
2006
ACM
15 years 6 months ago
Interactive 3D distance field computation using linear factorization
We present an interactive algorithm to compute discretized 3D Euclidean distance fields. Given a set of piecewise linear geometric primitives, our algorithm computes the distance...
Avneesh Sud, Naga K. Govindaraju, Russell Gayle, D...
94
Voted
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
15 years 6 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 6 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
100
Voted
DATE
2005
IEEE
146views Hardware» more  DATE 2005»
15 years 6 months ago
Nonuniform Banking for Reducing Memory Energy Consumption
Main memories can consume a large percentage of overall energy in many data-intensive embedded applications. The past research proposed and evaluated memory banking as a possible ...
Ozcan Ozturk, Mahmut T. Kandemir