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» Improving SHA-2 Hardware Implementations
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106
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PPOPP
2010
ACM
15 years 7 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
129
Voted
CODES
2005
IEEE
15 years 6 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
109
Voted
MSS
2003
IEEE
173views Hardware» more  MSS 2003»
15 years 5 months ago
Peabody: The Time Travelling Disk
Disk drives are now available with capacities on the order of hundreds of gigabytes. What has not become available is an easy way to manage storage. With installed machines locate...
Charles B. Morrey III, Dirk Grunwald
JSAC
2006
165views more  JSAC 2006»
15 years 14 days ago
ALPi: A DDoS Defense System for High-Speed Networks
Distributed denial-of-service (DDoS) attacks pose a significant threat to the Internet. Most solutions proposed to-date face scalability problems as the size and speed of the netwo...
P. E. Ayres, H. Sun, H. Jonathan Chao, Wing Cheong...
119
Voted
CVPR
2007
IEEE
16 years 2 months ago
A Human Action Recognition System for Embedded Computer Vision Application
In this paper, we propose a human action recognition system suitable for embedded computer vision applications in security systems, human-computer interaction and intelligent envi...
Hongying Meng, Nick Pears, Chris Bailey