1045 search results - page 74 / 209 » Improving SHA-2 Hardware Implementations |
89
Voted
EH
1999
IEEE
15 years 5 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
84
Voted
EUROMICRO
1999
IEEE
15 years 5 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
94
Voted
ASAP
2004
IEEE
15 years 4 months ago
2004
IEEE
IPSec is a suite of protocols that adds security to communications at the IP level. Protocols within the IPSec suite make extensive use of cryptographic algorithms. Since these al...
94
Voted
CASES
2008
ACM
15 years 2 months ago
2008
ACM
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
117
Voted
ASPDAC
2007
ACM
15 years 4 months ago
2007
ACM
Clock skew scheduling is a technique that intentionally introduces skews to memory elements to improve the performance of a sequential circuit. It was shown in [21] that the full ...