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CODES
2006
IEEE
15 years 3 months ago
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability
Reliability in embedded processors can be improved by control flow checking and such checking can be conducted using software or hardware. Proposed software-only approaches suffe...
Roshan G. Ragel, Sri Parameswaran
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
15 years 2 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
15 years 10 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
ICSE
2005
IEEE-ACM
15 years 9 months ago
Binary refactoring: improving code behind the scenes
We present Binary Refactoring: a software engineering technique for improving the implementation of programs without modifying their source code. While related to regular refactor...
Eli Tilevich, Yannis Smaragdakis
ICPR
2006
IEEE
15 years 10 months ago
Statistical Model for the Classification of the Wavelet Transforms of T-ray Pulses
This study applies Auto Regressive (AR) and Auto Regressive Moving Average (ARMA) modeling to wavelet decomposed terahertz pulsed signals to assist biomedical diagnosis and mail/p...
Bradley Ferguson, Brian Wai-Him Ng, Derek Abbott, ...