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EUROPAR
2010
Springer
14 years 9 months ago
Optimized On-Chip-Pipelined Mergesort on the Cell/B.E
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
Rikard Hultén, Christoph W. Kessler, Jö...
89
Voted
CCR
2000
113views more  CCR 2000»
14 years 9 months ago
TCP rate control
TCP congestion control 9] is designed for network stability, robustness and opportunistic use of network bu er and bandwidth resources on an end-to-end per-connection basis. Upon ...
Shrikrishna Karandikar, Shivkumar Kalyanaraman, Pr...
RTCSA
2006
IEEE
15 years 3 months ago
Systematic Security and Timeliness Tradeoffs in Real-Time Embedded Systems
Real-time embedded systems are increasingly being networked. In distributed real-time embedded applications, e.g., electric grid management and command and control applications, i...
Kyoung-Don Kang, Sang Hyuk Son
BMCBI
2010
183views more  BMCBI 2010»
14 years 9 months ago
SING: Subgraph search In Non-homogeneous Graphs
Background: Finding the subgraphs of a graph database that are isomorphic to a given query graph has practical applications in several fields, from cheminformatics to image unders...
Raffaele Di Natale, Alfredo Ferro, Rosalba Giugno,...
94
Voted
CODES
2005
IEEE
15 years 3 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...