110 search results - page 7 / 22 » Improving Transition Delay Test Using a Hybrid Method |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
1 The first path implicit and exact non–robust path delay fault grading technique for non–scan sequential circuits is presented. Non enumerative exact coverage is obtained, b...
SARA
2009
Springer
15 years 4 months ago
2009
Springer
We present algorithms for testing the satisfiability and finding the tightened transitive closure of conjunctions of addition constraints of the form ±x ± y ≤ d and bound co...
SAC
2008
ACM
14 years 9 months ago
2008
ACM
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed testing of high-speed embedded processors testing in an SoC system. For SBST, test rout...
DELTA
2006
IEEE
15 years 3 months ago
2006
IEEE
In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnec...
VMCAI
2005
Springer
15 years 3 months ago
2005
Springer
Bounded model checking (BMC) is an automatic verification method that is based on a finite unfolding of the system’s transition relation. BMC has been successfully applied, in ...