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VLSID
2007
IEEE
108views VLSI» more  VLSID 2007»
16 years 5 months ago
Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model
Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET mode...
Feng Wang 0004, Yuan Xie, R. Rajaraman, Balaji Vai...
ICASSP
2009
IEEE
15 years 12 months ago
Design of oversampled DFT modulated filter banks optimized for acoustic echo cancellation
This paper describes a method for designing oversampled DFT filter banks (FB) optimized for subband acoustic echo cancellation (AEC). For this application, the design requirements...
Qin Li, Wei-Ge Chen, Chao He, Henrique S. Malvar
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 9 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
CORR
2010
Springer
138views Education» more  CORR 2010»
15 years 5 months ago
A Framework for Interactive Work Design based on Digital Work Analysis and Simulation
Due to the flexibility and adaptability of human, manual handling work is still very important in industry, especially for assembly and maintenance work. Well-designed work operat...
Liang Ma, Wei Zhang, Huanzhang Fu, Yang Guo, Damie...
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CIKM
2007
Springer
15 years 11 months ago
Link analysis using time series of web graphs
Link analysis is a key technology in contemporary web search engines. Most of the previous work on link analysis only used information from one snapshot of web graph. Since commer...
Lei Yang, Lei Qi, Yan-Ping Zhao, Bin Gao, Tie-Yan ...