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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
16 years 13 days ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
CSREAESA
2003
15 years 7 months ago
Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
Friedhelm Stappert, Carsten Rust
DATE
2010
IEEE
163views Hardware» more  DATE 2010»
15 years 10 months ago
Efficient High-Level modeling in the networking domain
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
Christian Zebelein, Joachim Falk, Christian Haubel...
179
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ECBS
2004
IEEE
115views Hardware» more  ECBS 2004»
15 years 10 months ago
Supporting Evolutionary Development by Feature Models and Traceability Links
During their usage, software systems have to be changed constantly. If such changes are implemented in an incomplete or inconsistent way a loss of architectural quality will occur...
Matthias Riebisch
DAC
2006
ACM
16 years 7 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram