Sciweavers

5523 search results - page 107 / 1105
» Improving application performance with hardware data structu...
Sort
View
FCCM
2009
IEEE
134views VLSI» more  FCCM 2009»
15 years 1 months ago
Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants
Scheduling and partitioning of task graphs on reconfigurable hardware needs to be carefully carried out in order to achieve the best possible performance. In this paper, we demons...
Miaoqing Huang, Vikram K. Narayana, Tarek A. El-Gh...
ITC
2003
IEEE
92views Hardware» more  ITC 2003»
15 years 3 months ago
Infrastructure IP for Back-End Yield Improvement
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a botto...
L. Forli, Jean Michel Portal, Didier Née, B...
SBACPAD
2007
IEEE
157views Hardware» more  SBACPAD 2007»
15 years 4 months ago
Exploring Novel Parallelization Technologies for 3-D Imaging Applications
Multi-dimensional imaging techniques involve the processing of high resolution images commonly used in medical, civil and remote-sensing applications. A barrier commonly encounter...
Diego Rivera, Dana Schaa, Micha Moffie, David R. K...
DEBS
2010
ACM
15 years 1 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
CCR
2010
110views more  CCR 2010»
14 years 10 months ago
An improved analysis of the lossy difference aggregator
We provide a detailed analysis of the Lossy Difference Aggregator, a recently developed data structure for measuring latency in a router environment where packet losses can occur....
Hilary Finucane, Michael Mitzenmacher