Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a c...
Many opportunities for easy, big-win, program optimizations are missed by compilers. This is especially true in highly layered Java applications. Often at the heart of these misse...
Guoqing Xu, Nick Mitchell, Matthew Arnold, Atanas ...
This paper describes the design, implementation and performance of an open, high performance, dynamically extensible router under development at Washington University in St. Louis...
Fred Kuhns, John D. DeHart, Anshul Kantawala, Ralp...