5523 search results - page 175 / 1105 » Improving application performance with hardware data structu... |
138
Voted
ISCA
1994
IEEE
15 years 7 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
144
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PPOPP
2010
ACM
16 years 26 days ago
2010
ACM
To achieve high-performance on multicore systems, sharedmemory parallel languages must efficiently implement atomic operations. The commonly used and studied paradigms for atomici...
119
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FOCS
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a strongly history independent (SHI) hash table that supports search in O(1) worst-case time, and insert and delete in O(1) expected time using O(n) data space. This ma...
119
Voted
ICDE
1993
IEEE
15 years 7 months ago
1993
IEEE
This paper presents the design and implementation of a transaction manager embedded in a log-structured file system [11]. Measurements show that transaction support on a log-stru...
172
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TVCG
2012
13 years 6 months ago
2012
—This paper presents a volumetric modeling framework to construct a novel spline scheme called restricted trivariate polycube splines (RTP-splines). The RTP-spline aims to genera...