This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cach...
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
In discretization of a continuous variable its numerical value range is divided into a few intervals that are used in classification. For example, Na¨ıve Bayes can benefit from...
In some registration applications additional user knowledge is available, which can improve and accelerate the registration process, especially for non-rigid registration. This is ...
This paper proposes a low power technique, called SBR (Sign Bit Reduction) which may reduce the switching activity in multipliers as well as data buses. Utilizing the multipliers ...