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DATE
2006
IEEE
110views Hardware» more  DATE 2006»
15 years 10 months ago
Layout driven data communication optimization for high level synthesis
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer...
IPPS
2009
IEEE
15 years 11 months ago
Annotation-based empirical performance tuning using Orio
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
Albert Hartono, Boyana Norris, Ponnuswamy Sadayapp...
IJON
2006
109views more  IJON 2006»
15 years 4 months ago
Integrating the improved CBP model with kernel SOM
In this paper, we first design a more generalized network model, Improved CBP, based on the same structure as Circular BackPropagation (CBP) proposed by Ridella et al. The novelty ...
Qun Dai, Songcan Chen
ISPASS
2009
IEEE
15 years 11 months ago
Machine learning based online performance prediction for runtime parallelization and task scheduling
—With the emerging many-core paradigm, parallel programming must extend beyond its traditional realm of scientific applications. Converting existing sequential applications as w...
Jiangtian Li, Xiaosong Ma, Karan Singh, Martin Sch...
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 10 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...