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144
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IMS
2000
125views Hardware» more  IMS 2000»
15 years 8 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
15 years 9 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
163
Voted
HPCC
2009
Springer
15 years 9 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
IROS
2007
IEEE
144views Robotics» more  IROS 2007»
15 years 11 months ago
High precision PSD guided robot localization: Design, mapping, and position control
— This paper introduces our recently developed high precision robot localization system employing position sensitive detectors (PSD). A lateral effect PSD is an ideal position se...
S. Blank, Yantao Shen, Ning Xi, Chi Zhang, Uchechu...
SIGMETRICS
2010
ACM
160views Hardware» more  SIGMETRICS 2010»
15 years 9 months ago
RSIO: automatic user interaction detection and scheduling
We present RSIO, a processor scheduling framework for improving the response time of latency-sensitive applications by monitoring accesses to I/O channels and inferring when user ...
Haoqiang Zheng, Jason Nieh