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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 9 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
ICCD
2004
IEEE
131views Hardware» more  ICCD 2004»
16 years 1 months ago
3D Processing Technology and Its Impact on iA32 Microprocessors
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either f...
Bryan Black, Donald Nelson, Clair Webb, Nick Samra
143
Voted
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
15 years 10 months ago
Optimized decoding scheme for erroneous MPEG-4 FGS bitstream
—In this paper, a structure of a packet error resilient Fine Granularity Scalable MPEG-4 decoder is proposed. The performance of the proposed decoder is tested and tests are repe...
Janne Vehkaperä, Johannes Peltola
157
Voted
PKDD
2010
Springer
235views Data Mining» more  PKDD 2010»
15 years 2 months ago
Online Structural Graph Clustering Using Frequent Subgraph Mining
The goal of graph clustering is to partition objects in a graph database into different clusters based on various criteria such as vertex connectivity, neighborhood similarity or t...
Madeleine Seeland, Tobias Girschick, Fabian Buchwa...
137
Voted
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
15 years 10 months ago
Efficient Simulation of Synthesis-Oriented System Level Designs
Modeling for synthesis and modeling for simulation seem to be two competing goals in the context of C++-based modeling frameworks. One of the reasons is while most hardware system...
Rajesh K. Gupta, Sandeep K. Shukla, Nick Savoiu