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MICRO
2000
IEEE
98views Hardware» more  MICRO 2000»
15 years 7 months ago
Efficient conditional operations for data-parallel architectures
Many data-parallel applications, including emerging media applications, have regular structures that can easily be expressed as a series of arithmetic kernels operating on data st...
Ujval J. Kapasi, William J. Dally, Scott Rixner, P...
SBACPAD
2003
IEEE
103views Hardware» more  SBACPAD 2003»
15 years 8 months ago
Profiling and Optimization of Software-Based Network-Analysis Applications
A large set of tools for network monitoring and accounting, security, traffic analysis and prediction — more broadly, for network operation and management — require direct and...
Loris Degioanni, Mario Baldi, Fulvio Risso, Gianlu...
SIGMETRICS
2003
ACM
147views Hardware» more  SIGMETRICS 2003»
15 years 8 months ago
Effect of node size on the performance of cache-conscious B+-trees
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Richard A. Hankins, Jignesh M. Patel
MASCOTS
2008
15 years 4 months ago
Modeling Software Contention using Colored Petri Nets
Commercial servers, such as database or application servers, often attempt to improve performance via multithreading. Improper multi-threading architectures can incur contention, ...
Nilabja Roy, Akshay Dabholkar, Nathan Hamm, Lawren...
124
Voted
ICS
2007
Tsinghua U.
15 years 9 months ago
Tradeoff between data-, instruction-, and thread-level parallelism in stream processors
This paper explores the scalability of the Stream Processor architecture along the instruction-, data-, and thread-level parallelism dimensions. We develop detailed VLSI-cost and ...
Jung Ho Ahn, Mattan Erez, William J. Dally