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ISCA
2007
IEEE
177views Hardware» more  ISCA 2007»
15 years 4 months ago
Adaptive insertion policies for high performance caching
The commonly used LRU replacement policy is susceptible to thrashing for memory-intensive workloads that have a working set greater than the available cache size. For such applica...
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, ...
DATE
2010
IEEE
122views Hardware» more  DATE 2010»
15 years 3 months ago
SimTag: Exploiting tag bits similarity to improve the reliability of the data caches
— Though tag bits in the data caches are vulnerable to transient errors, few effort has been made to reduce their vulnerability. In this paper, we propose to exploit prevalent sa...
Jesung Kim, Soontae Kim, Yebin Lee
CLUSTER
2011
IEEE
13 years 9 months ago
Performance Characterization and Optimization of Atomic Operations on AMD GPUs
—Atomic operations are important building blocks in supporting general-purpose computing on graphics processing units (GPUs). For instance, they can be used to coordinate executi...
Marwa Elteir, Heshan Lin, Wu-chun Feng
ACISICIS
2005
IEEE
15 years 3 months ago
An Effective Cache Overlapping Storage Structure for SMT Processors
Simultaneous Multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle....
Liqiang He, Zhiyong Liu
ARC
2010
Springer
144views Hardware» more  ARC 2010»
15 years 4 months ago
QUAD - A Memory Access Pattern Analyser
In this paper, we present the Quantitative Usage Analysis of Data (QUAD) tool, a sophisticated memory access tracing tool that provides a comprehensive quantitative analysis of mem...
S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, K...