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HPCA
2009
IEEE
16 years 5 months ago
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Mainak Chaudhuri
PLDI
2004
ACM
15 years 10 months ago
Min-cut program decomposition for thread-level speculation
With billion-transistor chips on the horizon, single-chip multiprocessors (CMPs) are likely to become commodity components. Speculative CMPs use hardware to enforce dependence, al...
Troy A. Johnson, Rudolf Eigenmann, T. N. Vijaykuma...
DATE
2007
IEEE
95views Hardware» more  DATE 2007»
15 years 11 months ago
Memory bank aware dynamic loop scheduling
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
Mahmut T. Kandemir, Taylan Yemliha, Seung Woo Son,...
ISCA
2010
IEEE
216views Hardware» more  ISCA 2010»
15 years 3 months ago
The impact of management operations on the virtualized datacenter
Virtualization has the potential to dramatically reduce the total cost of ownership of datacenters and increase the flexibility of deployments for general-purpose workloads. If pr...
Vijayaraghavan Soundararajan, Jennifer M. Anderson
VLDB
2004
ACM
163views Database» more  VLDB 2004»
15 years 10 months ago
Compressing Large Boolean Matrices using Reordering Techniques
Large boolean matrices are a basic representational unit in a variety of applications, with some notable examples being interactive visualization systems, mining large graph struc...
David S. Johnson, Shankar Krishnan, Jatin Chhugani...