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ICCAD
1996
IEEE
92views Hardware» more  ICCAD 1996»
15 years 2 months ago
Generation of BDDs from hardware algorithm descriptions
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
Shin-ichi Minato
ECML
2006
Springer
15 years 1 months ago
Margin-Based Active Learning for Structured Output Spaces
In many complex machine learning applications there is a need to learn multiple interdependent output variables, where knowledge of these interdependencies can be exploited to impr...
Dan Roth, Kevin Small
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
15 years 3 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ISPD
2005
ACM
140views Hardware» more  ISPD 2005»
15 years 3 months ago
Are floorplan representations important in digital design?
Research in floorplanning and block-packing has generated a variety of data structures to represent spatial configurations of circuit modules. Much of this work focuses on the g...
Hayward H. Chan, Saurabh N. Adya, Igor L. Markov