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EUROPAR
2010
Springer
14 years 10 months ago
Efficient Address Mapping of Shared Cache for On-Chip Many-Core Architecture
Abstract. Performance of the on-chip cache is critical for processor. The multithread program model usually employed by on-chip many-core architectures may have effects on cache ac...
Fenglong Song, Dongrui Fan, Zhiyong Liu, Junchao Z...
ATAL
2003
Springer
15 years 2 months ago
Representation and reasoning for DAML-based policy and domain services in KAoS and nomads
To increase the assurance with which agents can be deployed in operational settings, we have been developing the KAoS policy and domain services. In conjunction with Nomads strong...
Jeffrey M. Bradshaw, Andrzej Uszok, Renia Jeffers,...
ICRE
1998
IEEE
15 years 1 months ago
Surfacing Root Requirements Interactions from Inquiry Cycle Requirements Documents
Systems requirements errors are numerous, persistent, and expensive. To detect such errors, and focus on critical ones during the development of a requirements document, we have d...
William N. Robinson, Suzanne D. Pawlowski
66
Voted
COR
2008
129views more  COR 2008»
14 years 9 months ago
Queues in DOCSIS cable modem networks
In this paper we determine the optimal fraction c of the uplink channel capacity that should be dedicated to the contention channel in a DOCSIS cable network in order to minimize ...
Joke Lambert, Benny Van Houdt, Chris Blondia
CAV
2003
Springer
155views Hardware» more  CAV 2003»
15 years 1 months ago
An Improved On-The-Fly Tableau Construction for a Real-Time Temporal Logic
Abstract. Temporal logic is popular for specifying correctness properties of reactive systems. Real-time temporal logics add the ability to express quantitative timing aspects. Tab...
Marc Geilen