71 search results - page 13 / 15 » Improving memory bank-level parallelism in the presence of p... |
105
click to vote
CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
We characterize the performance and power attributes of the conjugate gradient (CG) sparse solver which is widely used in scientific applications. We use cycle-accurate simulatio...
110
click to vote
IWMM
2010
Springer
15 years 4 months ago
2010
Springer
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
ICPP
2003
IEEE
15 years 5 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
158
click to vote
HPCA
2004
IEEE
16 years 8 hour ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...