71 search results - page 9 / 15 » Improving memory bank-level parallelism in the presence of p... |
IPPS
2009
IEEE
15 years 6 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
EUROPAR
2003
Springer
15 years 5 months ago
2003
Springer
We introduce a software/hardware scheme called the Field Array Compression Technique (FACT) which reduces cache misses due to recursive data structures. Using a data layout transfo...
CORR
2009
Springer
14 years 9 months ago
2009
Springer
Previous work has shown that there are two major complexity barriers in the synthesis of fault-tolerant distributed programs, namely generation of fault-span, the set of states re...
116
click to vote
IEEEPACT
2002
IEEE
15 years 4 months ago
2002
IEEE
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
HPCA
2008
IEEE
16 years 2 days ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...