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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 6 months ago
Hardware synthesis from guarded atomic actions with performance specifications
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...
Daniel L. Rosenband
SPAA
2012
ACM
13 years 2 days ago
A scalable framework for heterogeneous GPU-based clusters
GPU-based heterogeneous clusters continue to draw attention from vendors and HPC users due to their high energy efficiency and much improved single-node computational performance...
Fengguang Song, Jack Dongarra
GPC
2007
Springer
15 years 3 months ago
Towards Feasible and Effective Load Sharing in a Heterogeneous Computational Grid
A grid has to provide strong incentive for participating sites to join and stay in it. Participating sites are concerned with the performance improvement brought by the gird for th...
Kuo-Chan Huang, Po-Chi Shih, Yeh-Ching Chung
75
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HPCA
2005
IEEE
15 years 10 months ago
A Performance Comparison of DRAM Memory System Optimizations for SMT Processors
Memory system optimizations have been well studied on single-threaded systems; however, the wide use of simultaneous multithreading (SMT) techniques raises questions over their ef...
Zhichun Zhu, Zhao Zhang
ICASSP
2011
IEEE
14 years 1 months ago
Coordinated user scheduling in the multi-cell MIMO downlink
We propose a novel, coordinated user scheduling (CUS) algorithm for inter-cell interference (ICI) mitigation in the downlink of a multi-cell multi-user MIMO system. In the propose...
Nima Seifi, Michail Matthaiou, Mats Viberg