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CF
2005
ACM
15 years 1 months ago
Dynamic loop pipelining in data-driven architectures
Data-driven array architectures seem to be important alternatives for coarse-grained reconfigurable computing platforms. Their use has provided performance improvements over micro...
João M. P. Cardoso
ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 3 months ago
Software Versus Hardware Shared-Memory Implementation: A Case Study
We comparethe performance of software-supported shared memory on a general-purpose network to hardware-supported shared memory on a dedicated interconnect. Up to eight processors,...
Alan L. Cox, Sandhya Dwarkadas, Peter J. Keleher, ...
DAC
2003
ACM
16 years 18 days ago
Multilevel global placement with retiming
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
Jason Cong, Xin Yuan
BMCBI
2008
159views more  BMCBI 2008»
14 years 11 months ago
Multivariate hierarchical Bayesian model for differential gene expression analysis in microarray experiments
Background: Identification of differentially expressed genes is a typical objective when analyzing gene expression data. Recently, Bayesian hierarchical models have become increas...
Hongya Zhao, Kwok-Leung Chan, Lee-Ming Cheng, Hong...
HPCA
2002
IEEE
15 years 12 months ago
Evaluation of a Multithreaded Architecture for Cellular Computing
Cyclops is a new architecture for high performance parallel computers being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip...
Calin Cascaval, José G. Castaños, Lu...