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151
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CGO
2005
IEEE
15 years 10 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
161
Voted
CODES
2005
IEEE
15 years 10 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
161
Voted
CODES
2005
IEEE
15 years 10 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
COMPSAC
2005
IEEE
15 years 10 months ago
Two Variations to the mCESG Pollsterless E-Voting Scheme
— Over the past several years, the UK Government has piloted several new voting technologies during local authority elections. The mCESG pollsterless Remote Electronic Voting (RE...
Tim Storer, Ishbel Duncan
155
Voted
ISPASS
2005
IEEE
15 years 10 months ago
Anatomy and Performance of SSL Processing
A wide spectrum of e-commerce (B2B/B2C), banking, financial trading and other business applications require the exchange of data to be highly secure. The Secure Sockets Layer (SSL...
Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. ...
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