42 search results - page 7 / 9 » Improving superword level parallelism support in modern comp... |
ISCA
1999
IEEE
13 years 10 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
IPPS
2009
IEEE
14 years 1 months ago
2009
IEEE
DTA (Decoupled Threaded Architecture) is designed to exploit fine/medium grained Thread Level Parallelism (TLP) by using a distributed hardware scheduling unit and relying on exi...
APCSAC
2003
IEEE
13 years 10 months ago
2003
IEEE
Very Long Instruction Word (VLIW) architectures exploit instruction level parallelism (ILP) with the help of the compiler to achieve higher instruction throughput with minimal hard...
CCGRID
2003
IEEE
13 years 11 months ago
2003
IEEE
I/O bottlenecks are already a problem in many largescale applications that manipulate huge datasets. This problem is expected to get worse as applications get larger, and the I/O ...
SOFSEM
2010
Springer
14 years 3 months ago
2010
Springer
Programmers rely on programming idioms, design patterns, and workaround techniques to make up for missing programming language support. Evolving languages often address frequently ...