271 search results - page 11 / 55 » Improving the Average Delay of Sorting |
TCAD
1998
14 years 9 months ago
1998
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
ITC
2003
IEEE
15 years 2 months ago
2003
IEEE
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
71
Voted
SIPS
2007
IEEE
15 years 3 months ago
2007
IEEE
Unlike 1000BASE-T system, the far-end crosstalk (FEXT) must be suppressed by at least 20 dB to meet the high speed transmission requirement for 10GBASE-T. Without FEXT cancellatio...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Delay minimization continues to be an important objective in the design of high-performance computing system. In this paper, we present an effective methodology to guide the delay...