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SIGOPS
2010
179views more  SIGOPS 2010»
14 years 4 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 4 months ago
Hardware atomicity for reliable software speculation
Speculative compiler optimizations are effective in improving both single-thread performance and reducing power consumption, but their implementation introduces significant compl...
Naveen Neelakantam, Ravi Rajwar, Suresh Srinivas, ...
IEEEPACT
2009
IEEE
14 years 7 months ago
Cache Sharing Management for Performance Fairness in Chip Multiprocessors
Resource sharing can cause unfair and unpredictable performance of concurrently executing applications in Chip-Multiprocessors (CMP). The shared last-level cache is one of the mos...
Xing Zhou, Wenguang Chen, Weimin Zheng
MOVEP
2000
136views Hardware» more  MOVEP 2000»
15 years 1 months ago
UPPAAL - Now, Next, and Future
Uppaal is a tool for modeling, simulation and verification of real-time systems, developed jointly by BRICS at Aalborg University and the Department of Computer Systems at Uppsala ...
Tobias Amnell, Gerd Behrmann, Johan Bengtsson, Ped...
GRID
2007
Springer
15 years 1 months ago
Optimizing multiple queries on scientific datasets with partial replicas
We propose strategies to efficiently execute a query workload, which consists of multiple related queries submitted against a scientific dataset, on a distributed-memory system in...
Li Weng, Ümit V. Çatalyürek, Tahs...