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» Improving the Java memory model using CRF
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86
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FMCAD
2009
Springer
15 years 6 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
GECCO
2006
Springer
188views Optimization» more  GECCO 2006»
15 years 3 months ago
Dynamic multi-objective optimization with evolutionary algorithms: a forward-looking approach
This work describes a forward-looking approach for the solution of dynamic (time-changing) problems using evolutionary algorithms. The main idea of the proposed method is to combi...
Iason Hatzakis, David Wallace
EUROGRAPHICS
2010
Eurographics
15 years 8 months ago
HCCMeshes: Hierarchical-Culling oriented Compact Meshes
Hierarchical culling is a key acceleration technique used to efficiently handle massive models for ray tracing, collision detection, etc. To support such hierarchical culling, bo...
Tae-Joon Kim, Yongyoung Byun, Yongjin Kim, Bochang...
RE
2008
Springer
14 years 11 months ago
Generating Natural Language specifications from UML class diagrams
Early phases of software development are known to be problematic, difficult to manage and errors occurring during these phases are expensive to correct. Many systems have been deve...
Farid Meziane, Nikos Athanasakis, Sophia Ananiadou
102
Voted
DAC
2006
ACM
16 years 21 days ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu