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» Improving the Memory Bandwidth Utilization Using Loop Transf...
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83
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HPCA
2007
IEEE
16 years 18 hour ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
106
Voted
PDPTA
2000
15 years 1 months ago
Evaluation of Neural and Genetic Algorithms for Synthesizing Parallel Storage Schemes
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
Mayez A. Al-Mouhamed, Husam Abu-Haimed
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
14 years 11 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
ICS
1999
Tsinghua U.
15 years 3 months ago
Nonlinear array layouts for hierarchical memory systems
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
Siddhartha Chatterjee, Vibhor V. Jain, Alvin R. Le...
86
Voted
EWC
2000
97views more  EWC 2000»
14 years 11 months ago
Improving the Rationale Capture Capability of QFD
The goals of Design Rationale Capture (DRC) are improving design quality and reducing design time. These general goals have led to the design of many DRC techniques originating fro...
Yoram Reich