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215
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ASPLOS
2009
ACM
15 years 11 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
93
Voted
CLUSTER
2007
IEEE
15 years 2 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
105
Voted
TCAD
2008
114views more  TCAD 2008»
14 years 10 months ago
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...
ATAL
2006
Springer
15 years 2 months ago
Synergistic integration of agent technologies for military simulation
To perform large-scale coordination in real-world environments requires that many individually complex technologies come together to form integrated solutions. In this paper, we p...
Sean Owens, Paul Scerri, Robin Glinton, Bin Yu, Ka...
ISLPED
2007
ACM
57views Hardware» more  ISLPED 2007»
14 years 11 months ago
Resource area dilation to reduce power density in throughput servers
Throughput servers using simultaneous multithreaded (SMT) processors are becoming an important paradigm with products such as Sun's Niagara and IBM Power5. Unfortunately, thr...
Michael D. Powell, T. N. Vijaykumar