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MICRO
2007
IEEE
150views Hardware» more  MICRO 2007»
15 years 6 months ago
Leveraging 3D Technology for Improved Reliability
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
Niti Madan, Rajeev Balasubramonian
GLOBECOM
2007
IEEE
15 years 4 months ago
CAC for Multibeam Opportunistic Schemes in Heterogeneous WiMax Systems Under QoS Constraints
Spatial scheduling in a heterogeneous WiMax Downlink channel, based on partial Channel State Information at the Transmitter (CSIT), is carried out through a multibeam opportunistic...
Nizar Zorba, Ana I. Pérez-Neira
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
15 years 7 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
102
Voted
SC
2009
ACM
15 years 7 months ago
Age based scheduling for asymmetric multiprocessors
Asymmetric (or Heterogeneous) Multiprocessors are becoming popular in the current era of multi-cores due to their power efficiency and potential performance and energy efficienc...
Nagesh B. Lakshminarayana, Jaekyu Lee, Hyesoon Kim
98
Voted
CGO
2004
IEEE
15 years 4 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...