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HPCA
2000
IEEE
15 years 1 months ago
Improving the Throughput of Synchronization by Insertion of Delays
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
Ravi Rajwar, Alain Kägi, James R. Goodman
ISCA
1998
IEEE
115views Hardware» more  ISCA 1998»
15 years 1 months ago
Improving the Throughput of a Pipeline by Insertion of Delays
Janak H. Patel, Edward S. Davidson
ICC
2008
IEEE
141views Communications» more  ICC 2008»
15 years 4 months ago
Delay Optimization in Cooperative Relaying with Cyclic Delay Diversity
— Cooperative relaying has recently been recognized as an alternative to MIMO in a typical multi cellular environment. Inserting random delays at the non-regenerative fixed rela...
S. Ben Slimane, Xuesong Li, Bo Zhou, Nauroze Syed,...
ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
15 years 6 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
NOCS
2010
IEEE
14 years 7 months ago
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
Tushar N. K. Jain, Paul V. Gratz, Alexander Sprint...