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MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 5 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
STORAGESS
2006
ACM
15 years 5 months ago
Using free web storage for data backup
Backing up important data is crucial. A variety of causes can lead to data loss, such as disk failures, administration errors, virus infiltration, theft, and physical damage to e...
Avishay Traeger, Nikolai Joukov, Josef Sipek, Erez...
CODES
2005
IEEE
15 years 5 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
INFOCOM
2005
IEEE
15 years 5 months ago
Minimum energy accumulative routing in wireless networks
— In this paper, we propose to address the energy efficient routing problem in multi-hop wireless networks with accumulative relay. In the accumulative relay model, partially ov...
Jiangzhuo Chen, Lujun Jia, Xin Liu, Guevara Noubir...
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 5 months ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood