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ICPP
2003
IEEE
15 years 4 months ago
2003
IEEE
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
SAC
2006
ACM
15 years 5 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
CVPR
2010
IEEE
15 years 7 months ago
2010
IEEE
Graph cuts methods are at the core of many state-of-theart algorithms in computer vision due to their efficiency in computing globally optimal solutions. In this paper, we solve t...
HAPTICS
2008
IEEE
14 years 11 months ago
2008
IEEE
The performance of haptic application is highly sensitive to communication delays and losses of data. It implies several constraints in developing networked haptic applications. Th...
ASAP
2006
IEEE
15 years 5 months ago
2006
IEEE
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...