Sciweavers

661 search results - page 10 / 133
» Increasing Processor Performance by Implementing Deeper Pipe...
Sort
View
105
Voted
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 1 months ago
Instruction Cache Fetch Policies for Speculative Execution
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grun...
ASPLOS
2004
ACM
15 years 2 months ago
Continual flow pipelines
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkar...
102
Voted
LCN
2005
IEEE
15 years 3 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
70
Voted
DSN
2005
IEEE
15 years 3 months ago
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...
Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, ...
IC
2004
14 years 11 months ago
Optimizing Performance of Web Services with Chunk-Overlaying and Pipelined-Send
The performance of a Web service is primarily dependent on the design and implementation of its SOAP toolkit. SOAP is widely implemented using HTTP as the transport protocol and X...
Nayef Abu-Ghazaleh, Madhusudhan Govindaraju, Micha...