661 search results - page 36 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
IWCC
1999
IEEE
15 years 4 months ago
1999
IEEE
In this paper, we present techniques and algorithms to improve the performance of various communication patterns on message-passing platforms where, for reasons of safety, user-le...
MICRO
1998
IEEE
15 years 4 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
MOBICOM
1996
ACM
15 years 4 months ago
1996
ACM
The CPU is one of the major power consumers in a portable computer, and considerable power can be saved by turning off the CPU when it is not doing useful work. In Apple's Ma...
MICRO
2000
IEEE
14 years 11 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
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FPL
2006
Springer
15 years 3 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...