661 search results - page 37 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
CODES
2001
IEEE
15 years 3 months ago
2001
IEEE
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
124
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SC
2004
ACM
15 years 5 months ago
2004
ACM
This paper presents a parallel visualization pipeline implemented at the Pittsburgh Supercomputing Center (PSC) for studying the largest earthquake simulation ever performed. The ...
110
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ANCS
2007
ACM
15 years 3 months ago
2007
ACM
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
107
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DSD
2005
IEEE
15 years 5 months ago
2005
IEEE
An implementation of an algorithm for string matching, commonly used in DNA string analysis, using configurable technology is proposed. The design of the circuit allows for pipeli...
FPL
2008
Springer
15 years 1 months ago
2008
Springer
Due to continuous improvements in the resources available on FPGAs, it is becoming increasingly possible to accelerate floating point algorithms. The solution of a system of linea...