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IPPS
1999
IEEE
15 years 4 months ago
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
ICCD
2000
IEEE
93views Hardware» more  ICCD 2000»
15 years 8 months ago
Cheap Out-of-Order Execution Using Delayed Issue
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
J. P. Grossman
INFOCOM
1998
IEEE
15 years 4 months ago
Routing Lookups in Hardware at Memory Access Speeds
Increased bandwidth in the Internet puts great demands on network routers; for example, to route minimum sized Gigabit Ethernet packets, an IP router must process about packets pe...
Pankaj Gupta, Steven Lin, Nick McKeown
ASPLOS
1992
ACM
15 years 3 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
15 years 4 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata