661 search results - page 46 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
ISCA
1998
IEEE
15 years 4 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
SIGGRAPH
1999
ACM
15 years 4 months ago
1999
ACM
With fast 3D graphics becoming more and more available even on low end platforms, the focus in hardware-accelerated rendering is beginning to shift towards higher quality renderin...
ISCA
1989
IEEE
15 years 3 months ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
101
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CLUSTER
2006
IEEE
15 years 5 months ago
2006
IEEE
IP routers are now increasingly expected to do more than just traditional packet forwarding – they must be extensible as well as scalable. It is a challenge to design a router a...
119
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INTENSIVE
2009
IEEE
15 years 6 months ago
2009
IEEE
In this paper an optimized k-means implementation on the graphics processing unit (GPU) is presented. NVIDIA’s Compute Unified Device Architecture (CUDA), available from the G8...