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SAMOS
2004
Springer
15 years 5 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
15 years 5 months ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
TPDS
2008
124views more  TPDS 2008»
14 years 11 months ago
Efficient Breadth-First Search on the Cell/BE Processor
Multicore processors are an architectural paradigm shift that promises a dramatic increase in performance. But, they also bring an unprecedented level of complexity in algorithmic ...
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Pe...
WMPI
2004
ACM
15 years 5 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...
DATE
2007
IEEE
134views Hardware» more  DATE 2007»
15 years 6 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra