661 search results - page 62 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
112
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ASAP
2004
IEEE
15 years 7 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
116
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SIPS
2008
IEEE
15 years 9 months ago
2008
IEEE
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture f...
122
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SIGMETRICS
1996
ACM
15 years 7 months ago
1996
ACM
A large and increasing gap exists between processor and memory speeds in scalable cache-coherent multiprocessors. To cope with this situation, programmers and compiler writers mus...
151
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JPDC
2010
15 years 1 months ago
2010
—We present the design and implementation of a parallel exact inference algorithm on the Cell Broadband Engine (Cell BE). Exact inference is a key problem in exploring probabilis...
113
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AHS
2007
IEEE
15 years 3 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...