661 search results - page 72 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
122
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ICCD
2007
IEEE
15 years 3 months ago
2007
IEEE
The emerging trend of larger number of cores or processors on a single chip in the server, desktop, and mobile notebook platforms necessarily demands larger amount of on-chip last...
110
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MICRO
2003
IEEE
15 years 5 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
138
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PADS
1999
ACM
15 years 4 months ago
1999
ACM
We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important...
LCTRTS
2007
Springer
15 years 6 months ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
CODES
2005
IEEE
15 years 5 months ago
2005
IEEE
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...