661 search results - page 97 / 133 » Increasing Processor Performance by Implementing Deeper Pipe... |
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
DAC
2008
ACM
16 years 27 days ago
2008
ACM
The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on paralle...
VIIP
2001
15 years 1 months ago
2001
Graphics cards exercise increasingly more computing power and are highly optimized for high data transfer volumes. In contrast typical workstations perform badly when data exceeds...
ICPP
1999
IEEE
15 years 4 months ago
1999
IEEE
Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, th...
IWMM
2010
Springer
15 years 3 months ago
2010
Springer
Concurrent and incremental collectors require barriers to ensure correct synchronisation between mutator and collector. The overheads imposed by particular barriers on particular ...