Sciweavers

661 search results - page 98 / 133
» Increasing Processor Performance by Implementing Deeper Pipe...
Sort
View
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
15 years 2 days ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CGO
2010
IEEE
15 years 6 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
HPCA
1996
IEEE
15 years 4 months ago
Improving Release-Consistent Shared Virtual Memory Using Automatic Update
Shared virtual memory is a software technique to provide shared memory on a network of computers without special hardware support. Although several relaxed consistency models and ...
Liviu Iftode, Cezary Dubnicki, Edward W. Felten, K...
RTSS
2006
IEEE
15 years 6 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
CISIS
2008
IEEE
15 years 6 months ago
On the Potential of NoC Virtualization for Multicore Chips
As the end of Moores-law is on the horizon, power becomes a limiting factor to continuous increases in performance gains for single-core processors. Processor engineers have shifte...
Jose Flich, Samuel Rodrigo, José Duato, Tho...