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» Increasing analog programmability in SoCs
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DATE
2008
IEEE
112views Hardware» more  DATE 2008»
15 years 4 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 1 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
DAC
2004
ACM
15 years 10 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
DAC
2006
ACM
15 years 10 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
FPL
2004
Springer
154views Hardware» more  FPL 2004»
15 years 3 months ago
High Performance True Random Number Generator in Altera Stratix FPLDs
Abstract. The paper presents a high performance True Random Number Generator (TRNG) embedded in Altera Stratix Field Programmable Logic Devices (FPLDs). As a source of randomness, ...
Viktor Fischer, Milos Drutarovský, Martin S...