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ARC
2008
Springer
115views Hardware» more  ARC 2008»
14 years 11 months ago
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applica...
Antonio Roldao Lopes, George A. Constantinides
PACS
2000
Springer
110views Hardware» more  PACS 2000»
15 years 1 months ago
Compiler-Directed Dynamic Frequency and Voltage Scheduling
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
RT
2001
Springer
15 years 2 months ago
Real-Time Occlusion Culling with a Lazy Occlusion Grid
We present a new conservative image-based occlusion culling method to increase the speed of hardware accelerated rendering of very complex general scenes which may consist of mill...
Heinrich Hey, Robert F. Tobler, Werner Purgathofer
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 4 months ago
Design flow for embedded FPGAs based on a flexible architecture template
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
B. Neumann, Thorsten von Sydow, Holger Blume, Tobi...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
15 years 6 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh