65 search results - page 11 / 13 » Increasing hardware efficiency with multifunction loop accel... |
ICCD
2000
IEEE
15 years 6 months ago
2000
IEEE
In superscalar architectures, out-of-order issue mechanisms increase performance by dynamically rescheduling instructions that cannot be statically reordered by the compiler. Whil...
MICRO
1998
IEEE
15 years 1 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
ASAP
2004
IEEE
15 years 1 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
BMCBI
2010
14 years 9 months ago
2010
Background: Solving bioinformatics tasks often requires extensive computational power. Recent trends in processor architecture combine multiple cores into a single chip to improve...
EGH
2010
Springer
14 years 7 months ago
2010
Springer
This paper proposes a massively parallel hardware architecture for efficient tracing of incoherent rays, e.g. for global illumination. The general approach is centered around hier...