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FPL
2001
Springer
123views Hardware» more  FPL 2001»
15 years 2 months ago
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines
This paper presents new achievements on the automatic mapping of algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable ...
João M. P. Cardoso, Horácio C. Neto
TVLSI
2008
115views more  TVLSI 2008»
14 years 9 months ago
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
Kieron Turkington, Turkington A. Constantinides, K...
AFRICACRYPT
2009
Springer
14 years 7 months ago
Efficient Acceleration of Asymmetric Cryptography on Graphics Hardware
Graphics processing units (GPU) are increasingly being used for general purpose computing. We present implementations of large integer modular exponentiation, the core of public-ke...
Owen Harrison, John Waldron
DAC
2008
ACM
15 years 10 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
IESS
2007
Springer
124views Hardware» more  IESS 2007»
15 years 3 months ago
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
: Hardware/software partitioning moves software kernels from a microprocessor to custom hardware accelerators. We consider advanced implementation options for accelerators, greatly...
Scott Sirowy, Frank Vahid