65 search results - page 7 / 13 » Increasing hardware efficiency with multifunction loop accel... |
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper introduces an efficient multithreaded synchronous dataflow (SDF) scheduler that can significantly reduce the running time of multi-rate SDF simulations on multiprocesso...
CASES
2007
ACM
15 years 1 months ago
2007
ACM
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
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FPGA
2004
ACM
15 years 3 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
ISSS
1999
IEEE
15 years 1 months ago
1999
IEEE
Code generation methods for digital signal processors are increasingly hampered by the combination of tight timing constraints imposed by the algorithms and the limited capacity o...
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...